In a semiconductor storage device that has an IO pin for receiving a strobe signal that decides input/output timing in data input/output, an output signal of an initial-stage circuit of the strobe signal at the IO pin, and an output signal of another initial-stage circuit of a driver pin which is separately provided from the IO pin, are interchanged in a mode setting or test function.
FIG. 6 illustrates an example of a typical configuration of a semiconductor storage device [DDR (Double Data Rate) SDRAM (Synchronous DRAM)] of the related art. As shown in FIG. 6, the device includes:
a plurality (n+1) of initial-stage circuits DI provided in correspondence with input/output terminals DQ0 to DQn, respectively, and comprising receivers (input buffers) having inputs DIN connected to input/output terminal data DQ0 to DQn, respectively, and outputting respective ones of signals IDQT0 to IDQTn from output terminals IDQT upon comparing the data with a reference voltage VREF;
an initial-stage circuit SI provided in correspondence with an input/output terminal DQS and comprising a receiver circuit for receiving a strobe signal DQS at an input DIN and outputting IDQS upon comparing the strobe signal with the reference voltage VREF;
an initial-stage circuit MI provided in correspondence with an input terminal DM and comprising a receiver for receiving a DM signal as an input and outputting IDM upon comparing the input with the reference voltage VREF;
a plurality of latch circuits DLD for receiving respective ones of the signals IDQT0 to IDQTn from the initial-stage circuits DI as inputs, latching these signals in response to IDQS and outputting latch data (DIR0, DIF0), . . . , (DIRn, DIFn); and
a latch circuit DLM for outputting latch data (DMR, DMF) that is the result of latching IDM from the initial-stage circuit MI at the timings of rising and falling edges of IDQS. Meanwhile, there is adopted such a notation that R and F provided in a last position or in a position preceding to a last index number of the signal names in data latch circuits indicate signals sampled responsive to rising and falling edges of latch timing signal, respectively.
The data strobe signal (DQS) is a bidirectional strobe signal and functions as a reference clock at the time of data input/output. At the time of a read cycle, edges (rising and falling edges) of DQS coincide with edges of read data. At the time of a write cycle, a controller (not shown) controls the data strobe signal (DQS), which is synchronized to a clock signal and the DDR-SRAM captures the data based upon the data strobe signal (DQS).
Further, DM is a write-mask enable signal that masks input data when it is at the high level. The input/output terminals DQ0 to DQn and DQS are connected to associated IO pins of a semiconductor test equipment (not shown), and the input terminal DM is connected to a driver pin of the semiconductor test equipment.
In a semiconductor test equipment or test board, an IO pin involves more wiring and load for a comparator than a driver pin or an IO pin. By the way, a driver pin of the semiconductor test equipment is usually connected to an input terminal of a device under test (DUT) and an IO driver pin of the semiconductor test equipment is connected to output and input terminals or an IO terminal of the device.
The input waveform of an IO pin having a heavy load has a slope [(amount of change in voltage)/(unit time)] smaller and less steep than that of the input waveform of the driver pin.
Consequently, in case of high speed operation, the amplitude of the input signal supplied to the test board from the semiconductor test equipment is of a level less than that set by a program or the like.
Further, since the slope of the waveform of the input signal supplied to the test board from the semiconductor test equipment is small, the input signal contains a large error referred to as jitter. This becomes more conspicuous in case of high speed operation with a large input amplitude.
Patent Document 1 discloses an arrangement for changing over an internal signal. Specifically, the arrangement suppresses an increase in number of terminals by assigning a mask address signal IDQM as is or a mask address signal obtained by decoding this signal to address signals that accompany a decrease in input/output data terminals when a test mode is in effect. Specifically, a test-mode activation signal is supplied internally as an internal mask decode signal when at the high level. When the test-mode activation signal is at the low level, an internal address mask signal is supplied internally as is as an in-phase signal. Further, Patent Document 2 discloses an arrangement in which buffer means is connected in series between an initial-stage circuit and a latch circuit. However, in Patent Documents 1 and 2, there is not disclosed any arrangement of reducing error in a measurement system for measuring the setup and hold characteristics of data, ascribable to the fact that the IO pin has a blunter waveform than the waveform of the driver pin.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-P2003-151300A
[Patent Document 2] Japanese Patent Kokai Publication No. JP-P2000-231787A
The following analysis is given by the present invention. In a semiconductor test equipment, only a driver controller need be provided for a driver pin. On the other hand, an IO pin involves the inclusion of a driver controller and a comparator controller. Consequently, jitter involving IO pins is generally set larger than jitter involving the driver pin.
Accordingly, the slopes of waveforms of a data signal and data strobe signal from IO pins of the semiconductor test equipment are both small and the amounts of jitter of both signals are large. As a result, a device under test (DUT) cannot capture a data signal received at an IO pin thereof responsive to a data strobe signal received at an IO pin thereof under accurate conditions. A problem which arises, therefore, is that accurate input setup and hold characteristics cannot be measured.
In relation to sampling by a latch circuit of a data signal DQ/write mask-enable signal DM based upon a data strobe signal DQS in a DDR-SDRAM, if it is attempted to capture DQ/DM data at high speed by DQS, which is received at an IO pin, the input signal of DQS will not reach the preset level, as mentioned above. In addition, since there will be a great amount of jitter, the output signal of the initial-stage circuit (receiver circuit) of the corresponding signal also will contain a large amount of jitter.
Similarly, since the data signal DQ sampled also is received at an IO pin, jitter is great and the setup and hold characteristics decided by IO pins for both DQ and DQS signals exhibiting large amounts of jitter are shifted from the correct characteristics.